/////////////////////////////////////////////////////////////////////
////                                                             ////
////  Author: Eyal Hochberg                                      ////
////          eyal@provartec.com                                 ////
////                                                             ////
////  Downloaded from: http://www.opencores.org                  ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2010 Provartec LTD                            ////
//// www.provartec.com                                           ////
//// info@provartec.com                                          ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
//// This source file is free software; you can redistribute it  ////
//// and/or modify it under the terms of the GNU Lesser General  ////
//// Public License as published by the Free Software Foundation.////
////                                                             ////
//// This source is distributed in the hope that it will be      ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied  ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR     ////
//// PURPOSE.  See the GNU Lesser General Public License for more////
//// details. http://www.gnu.org/licenses/lgpl.html              ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
//---------------------------------------------------------
//-- File generated by RobustVerilog parser
//-- Version: 1.0
//-- Invoked Fri Mar 25 23:36:56 2011
//--
//-- Source file: dma_ch_reg_params.v
//---------------------------------------------------------


  
   parameter              CMD_LINE0      = 8'h00;
   parameter              CMD_LINE1      = 8'h04;
   parameter              CMD_LINE2      = 8'h08;
   parameter              CMD_LINE3      = 8'h0C;
   parameter              STATIC_LINE0   = 8'h10;
   parameter              STATIC_LINE1   = 8'h14;
   parameter              STATIC_LINE2   = 8'h18;
   parameter              STATIC_LINE3   = 8'h1C;
   parameter              STATIC_LINE4   = 8'h20;
   
   parameter              RESTRICT       = 8'h2C;
   parameter              RD_OFFSETS     = 8'h30;
   parameter              WR_OFFSETS     = 8'h34;
   parameter              FIFO_FULLNESS  = 8'h38;
   parameter              CMD_OUTS       = 8'h3C;
   
   parameter              CH_ENABLE      = 8'h40;
   parameter              CH_START       = 8'h44;
   parameter              CH_ACTIVE      = 8'h48;
   parameter              CH_CMD_COUNTER = 8'h50;
                 
   parameter               INT_RAWSTAT    = 8'hA0;
   parameter               INT_CLEAR      = 8'hA4;
   parameter               INT_ENABLE     = 8'hA8;
   parameter               INT_STATUS     = 8'hAC;


